Code generation for a Multiple Clock design supports the following compilation targets:
- HDL Netlist
- IP catalog
- Synthesized Checkpoint
The following figure shows a screen shot of the top-level hardware.
The top level exposes the same number of clock ports as there are clock domains. These can be driven by a variety of AMD clocking constructs such as MMCM, PLL and so on. It is assumed that these clocks are completely asynchronous and the following period constraints are created.
These are the only constraints that you require because only FIFO or Dual Port RAM are allowed. These have any additional clock domain constraints embedded in the IP.