Calculating Latency Between AIE Ports - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

The AIE simulation is a cycle-approximate simulation, which means it can be used to estimate the latency between input and output ports of the AI Engine subsystem. This latency calculation can be displayed in Vitis Model Composer. To achieve this, run AIE simulation from the Analyze tab of the Model Composer Hub block with the Collect trace data for Vitis Analyzer option enabled. Then, do the following to select AI Engine subsystem ports and calculate the latency:

  1. On the Simulink canvas, select one input to the AI Engine subsystem and one output from the AI Engine subsystem.
    Note: To select multiple signals on the Simulink canvas, hold down the Shift button while selecting the signals.
  2. Right-click on the selected signals and select (AMD) AIE Compute Latency.
Figure 1. AIE Compute Latency

In the image above, pfa1008 is an AI Engine subsystem.

If AIE simulation has been previously run on this design, Vitis Model Composer will display the first sample latency, last sample latency, and average latency between the two selected ports.

Figure 2. AIE Latency Display

Latency can fluctuate over the course of a simulation, but it generally converges to a stable value over time.