HWCosim allows you to partially or fully offload the most compute intensive portion of a model into the actual target FPGA platform. The host system provides the stimulus to the model via the co-simulation interface (typically JTAG) and post-processes the response. This methodology is useful for validating the correctness of the generated hardware design on the target platform itself. It also improves the simulation time during model verification in hardware co-verification scenarios.
MATLAB/Simulink with Vitis Model Composer currently supports two variants of HWCosim: GUI-based and MATLAB M-script-based.
The GUI-based variant runs under the control of the Simulink scheduler. This can only progress one clock cycle at a time due to the potential for feedback loops in the model.
The second variant is MATLAB M-script based simulation under Model Composer control (M-HWCosim). This is commonly used in test benches produced as collateral during the bitstream generation from the Model Composer Hub block. These test benches are typically feedback-free and come with a-priori known input that can be transferred to the device in larger batches.