Enabling burst data transfer mode in the Vitis Model Composer Hub block replaces non-clock input and output registers with "n"-entry FIFOs. You can select "n" (FIFO depth), which is useful for trading off performance versus FPGA block RAM resource use.
Figure 1. Burst Mode
Enabling Burst Mode allows the M-HWCosim scheduler to do the following:
- "Burst write" a time-sequence of "n" values into each input FIFO,
- Run the clock for a number of cycles determined by the rate of input/output ports and the FIFO depths, and
- Capture the resulting output in the output FIFOs.
- After the batch runs, the scheduler proceeds to "burst read" the contents of the output FIFOs into a MATLAB array. Here, you can check it against expected data.
Figure 2. Burst Mode Flow
This batch processing of time samples allows for better packing of data into JTAG sequences, significantly reducing overhead.