To simplify super sample rate (SSR) designs, Vitis Model Composer supports bundling multiple SSR lanes into a single matrix signal. Within the AI Engine DSPLib, many blocks provide the option to Inherit from number of input columns when configuring SSR. When you select this option, an m×n input matrix to the block is interpreted as n parallel lanes. Multiple AI Engine DSPLib blocks can be connected using a single mxn signal, reducing model clutter.
At AI Engine subsystem boundaries, the tool determines how to interpret 2D signals by tracing connectivity from each input or output port to the terminal producer or consumer inside the subsystem. During this trace, interface pass-through elements such as PLIO, FIFO, To Fixed Size, and To Variable Size are skipped. When a terminal AI Engine block is found, its capabilities determine interpretation; if the terminal block supports SSR, the m×n container is treated as multichannel SSR data; if it does not, the same m×n container is treated as a single-channel 2D matrix.
For more information on configuring DSP library blocks, refer to the individual block help pages.