Black Box Clocking - Black Box Clocking - 2026.1 English - UG1483

To import a synchronous or asynchronous black box module, you must tell Model Composer information about the module's clocking in the configuration M-function. Model Composer treats clock and clock enables differently than other types of ports. An imported module's clock port requires a clock enable port, and vice versa. In other words, you must define clock and clock enables as a pair, and they must exist as a pair in the imported module. This is true for both single synchronous clock and multiple independent clock designs.

SysgenBlockDescriptor provides a method called addClkCEPair. You can use this to define clock, clock enable, and the associated clock period using clock sub-system domain. You do not need to proivide clock domain information for synchronous single clock designs.

The first parameter defines the name of the clock port (as it appears in the module). The second parameter defines the name of the clock enable port (also as it appears in the module).

The clock and clock-enable port names must use the following naming conventions:

• The clock port must contain the substring clk.
• The clock enable must contain the substring ce.
• The strings containing the substrings clk and ce must be the same, such as: my_clk_1 and my_ce_1.

The third parameter defines the rate relationship between the clock and the clock-enable port. The rate parameter is not a Simulink® sample rate. Instead, this parameter tells Model Composer the relationship between the clock sample period, and the desired clock enable sample period. The rate parameter is an integer value that defines the ratio between the clock rate and the corresponding clock enable rate.

For multiple independent clock designs, the fourth and fifth optional parameters are mandatory.

The fourth parameter holds a "Boolean" value to define whether the clock and clock enable pair ties to ground. If you set it to true, simulation ties both clock and clock enable to ground. Setting it to false activates clock and clock enable rate transitions.

The fifth parameter defines the clock period for the corresponding clock-clock enable pair. You must use the 'clockDomain' property of the black box "SysgenPortDescriptor" to set the clock periods for multiple independent clock designs.

Example:

rate_data = this_block.port('<port_name>').rate;
clkDomain_data = this_block.port(<port_name>).clockDomain;
this_block.addClkCEPair('clk',ce',rate_data, false, clkDomain_data);