Simulations in Vitis Model Composer are bit-true and cycle-true. A bit-true simulation means that at the boundaries (that is, interfaces between Model Composer HDL blocks and non-HDL blocks), a value produced in simulation is bit-for-bit identical to the corresponding value produced in hardware. A cycle-true simulation produces corresponding values at corresponding times at the boundaries.
The boundaries of the design are the points at which Model Composer HDL gateway blocks exist. When a design is translated into hardware, Gateway In (respectively, Gateway Out) blocks become top-level input (resp., output) ports.