You can find HDL blocks with AXI4-Stream interfaces in the Vitis Model Composer HDL Blockset Library, under DSP/AXI4. Blocks in this library display slightly differently from regular (non AXI4-Stream) blocks.
Port Groupings
Blocks that provide AXI4-Stream interfaces group AXI4-Stream channels together and color-code them. For example, on the
DDS compiler 6.0 block shown above, the input port data_tready, and the three output ports, data_tvalid, data_tdata_sine, data_tdata_cosine belong in the same AXI4-Stream channel. Similarly, the input ports
config_tvalid and config_tdata_pinc, and output port config_tready belong in the same AXI4-Stream channel. As does phase_tready, phase_tvalid, and
phase_tdata_phase_out.
Signals that are not part of any AXI4-Stream channels are the same background color as the block.
aresetn is an example.
Port Name Shortening
The following example shortens the AXI4-Stream signal names to improve readability on the block. Name shortening is purely cosmetic and when netlisting occurs, the full AXI4-Stream name is used. The tool enables name shortening by default. You can uncheck the Display shortened port names option in the block parameter dialog box to reveal the full name.
Breaking Out Multi-Channel TDATA
In AXI4-Stream, TDATA can contain
multiple channels of data. In Model Composer, the individual channels for TDATA are
broken out. So for example, the TDATA of port dout
below contains both real and imaginary components.
The breaking out of multi-channel TDATA does not add additional logic to the design and is done in Model Composer as a convenience. The data in each broken out TDATA port is also correctly byte-aligned.