Design creation and verification is exactly the same as
any other Vitis Model
Composer design that does not include an AXI4-Lite interface.
Consider the example_dds design
shown in the following figure.
This design contains a DDS Compiler where the two input
ports, config_tvalid and
config_tdata_pinc
control the output frequency.
The following figure shows the simulation results of this design which indicate both sine and cosine output separately.