AMBA AXI4 (Advanced eXtensible Interface 4) is the fourth generation of the AMBA interface defined and controlled by Arm® , and is adopted by AMD as the next-generation interconnect for FPGA designs. AMD and Arm® worked closely to ensure that the AXI4 specification addresses the needs of FPGAs.
AXI is an open interface standard. Many third-party IP vendors use it because it is public, royalty-free, and an industry standard.
The AMBA AXI4 interface connections are point-to-point and come in three different flavors: AXI4, AXI4-Lite Slave, and AXI4-Stream.
- AXI4 is a memory-mapped interface which support burst transactions
- AXI4-Lite Slave is a lightweight version of AXI4 and has a non-bursting interface
- AXI4-Stream is a high-performance streaming interface for unidirectional data transfers (from master to slave) with reduced signaling requirements (compared to AXI4). AXI4-Stream supports multiple channels of data on the same set of wires.
In this documentation, the following conventions apply:
- AXI4 refers to the AXI4 memory map interface,
- AXI4-Lite Slave and AXI4-Stream each refer to their respective flavor of the AMBA AXI4 interface.
- When referring to the collection of interfaces, the term AMBA AXI4 is used.
This section provides an introduction to AMBA AXI4 and draws attention to AMBA AXI4 details with respect to Vitis Model Composer. For more detailed information on the AMBA AXI4 specification, refer to the AMD AMBA-AXI4 documents. You can find these on the AMBA AXI4 Interface Protocol page on the AMD website.