The AIE to HDL block connects the output of AI Engine block with the input of HDL block. This block
accepts variable size signal from AI Engine
blocks along with the tready signal which indicates
whether the HDL domain can accept the data. This block inherits the input data type from
the input signal.
Note: If the HDL domain
tready signal remains low for an extended period, internal buffers in the
AIE to HDL block overflow and simulation stops.
Hardware functionality limits the bit width of the tdata output of the AIE to HDL block to 32,
64, and 128.Figure 1. AIE to HDL
Figure 2. AIE to HDL Parameters
