An AI Engine
kernel written using specialized intrinsic and imported into Vitis Model Composer can be used as part of a larger AMD Versal™
Adaptive SoC system design. In addition to
kernels operating on the AI Engines, you can specify
kernels to run on the programmable logic (PL) region of the device. You can write the PL
kernels using RTL or HLS C/C++ functions. The connection between AI Engine and the PL block routes through a physical channel interface
tile. Conceptually, the data width of the connections are 32 bits, 64 bits or 128
bits.
Model Composer allows connecting an AI Engine kernel to a HLS PL kernel only if the data types and complexities of these port matches. If the datatypes or complexities of the AI Engine kernel port and the PL kernel port do not match, use interface blocks to resolve the mismatch.
This chapter discusses interconnecting HDL blocks or HLS C/C++ functions with AI Engine kernels: