Description
This message reports a possible critical path error leading to timing violation in the user code.
Explanation
A timing violation is a path of operations requiring more time than the available clock cycle. Each operation may constitute a certain delay in the hardware, and if a set of operations' delays exceed the clock boundary, the HLS tool will inform the user of the violating clock cycle. If the design violates the clock cycle then the overall clock frequency rescales to the factor to accommodate the operations. At the HLS level these delays are estimated.
One of the main reasons for a timing violation is because of the II constraint. If the user specifies a strict II-1 constraint in the user code, the tool packs the operations back-to-back inside a clock boundary to achieve the required II. If a single operation in the user code exceeds the clock boundary then the tool will issue a timing violation.
To view a timing violation in the user code, see .
Solution
The solution to the timing violation is to relax the II constraint or refactor the user code to break the timing path.