The Vitis HLS scheduler schedules an operation on a resource after all its predecessor operations have completed execution. It schedules an operation according to these constraints:
- Timing constraints
- If the predecessor's output delay plus the operation's input
delay exceeds the clock period, it schedules the operation at least one clock
cycle after the cycle in which the last predecessor completed. Note: The output delay of the predecessor might include the delay of its predecessors scheduled in the same clock cycle.
- Dependence constraints
- If the combined delay does not exceed the clock period, it schedules the operation in the same clock cycle as the last predecessor.
Some operations have a latency > 0, meaning that they complete latency cycles after being scheduled. The latency of an operation is decided as follows:
- The scheduler can ensure that the longest combinational path within the resource implementing the operation does not exceed the clock period.
- You can use the latency option of the
bind_opandbind_storagepragmas.
Some constraints, specifically the latency or pipeline II constraints, can force two operations with a combined delay that exceeds the clock period to be scheduled in the same clock period, with the following warning.
WARNING: [HLS 200-880] The II Violation in module
'hls_complexf_exp_Pip_2' (loop 'VITIS_LOOP_456_1'):
Unable to enforce a carried dependence constraint (II = 4,
distance = 1, offset = 1) between
'select' operation 32 bit ('z', hlscaflib.c:457->hlscaflib.c:243) and
'fsub' operation 32 bit ('z', hlscaflib.c:459->hlscaflib.c:243).In this case, the best course of action is to investigate the combinational path highlighted in the GUI and to shorten it.