Resource Constraints - Resource Constraints - 2026.1 English - UG1448

Some operations have scheduler limitations that restrict the final II of a design due to the resource used by the operation. These limitations fall into the following categories:

1. Some types of non-scalar variable, limited by the read/write ports of the mapped resource:
   • Arrays mapped using interface, stream, or the bind_storage pragma
   • hls::stream, automatically mapped to a FIFO

     The precise details are as follows:

     • Each m_axi top pointer, streamed array, and hls::stream has one read and one write port.
     • Each block RAM or UltraRAM, if accessed only in sequential regions and managed as a ping-ping buffer between dataflow processes, has as many ports as specified by the corresponding bind_storage pragma:
       • You can explicitly add the pragma, or Vitis HLS can automatically infer it to satisfy the latency or II constraints.
       • In the case of a PIPO, the pragma specifies the number of ports available to each process:
         • RAM_1P has one port, which can be used either for reading or for writing in a given cycle.
         • RAM_2P has two ports, one supporting one read or write per cycle and one supporting one read per cycle.
         • RAM_S2P has two ports, one for reading and one for writing.
         • RAM_T2P has two ports, both supporting one operation per cycle.
         • RAM_1WnR has N+1 ports, where N can be chosen by the scheduler (1 for writing, N≤16 for reading).
         • ROM has N read ports, where N is chosen by the scheduler.
2. Pipelined or combinational operations, optionally limited by the allocation pragma (without it, the scheduler replicates them as needed to meet the required II):
   • Fixed point multipliers
   • Floating point operations
   • Calls to a non-inlined subfunction