Memory Port Resource Constraint (HLS 200-885) - Memory Port Resource Constraint (HLS 200-885) - 2026.1 English - UG1448

Description

This message explicitly informs you about insufficient memory ports allocated for a given array:

WARNING: [HLS 200-885] The II Violation in module 'kernel_Pipeline_target_loop' (loop 'target_loop'): Unable to schedule 'load' operation 32 bit ('u', ../kernel.cpp:32) on array 'b1' due to limited memory ports (II = 1). 
Please consider using a memory core with more ports or partitioning the array 'b1'.

Explanation

In this case, the source code looks like the following:

	int b0[N];
	int b1[N];
#pragma HLS BIND_STORAGE variable=b0 type=RAM_1P
#pragma HLS BIND_STORAGE variable=b1 type=RAM_1P
...
target_loop: for (int i = 0; i < N; i++) {
#pragma HLS pipeline II = 1
          int u, v;
          if (...) {
            u = b1[i];   // cycle 1
            v = b0[u-1]; // cycle 2
          } else {
            u = b0[i];   // cycle 1
            v = b1[u-1]; // cycle 2
          }
          cc[i] = v;
        }

In this case, both single-ported arrays b0 and b1 need to be accessed in both cycle 1 and cycle 2, so the minimum II is 2.

The Memory Schedule tab in the GUI schedule view for the failing loop highlights this by showing that there are two accesses for arrays b0 and b1, therefore requiring two cycles to be scheduled on a single port each.

Figure 1. Memory Schedule Tab

Recommendation

Using dual-ported arrays resolves the II issue:

#pragma HLS BIND_STORAGE variable=b0 type=RAM_2P

#pragma HLS BIND_STORAGE variable=b1 type=RAM_2P

For more information and for a definition of terms, refer to Pipeline II Violations.