Memory Port Resource Constraint (HLS 200-448) - Memory Port Resource Constraint (HLS 200-448) - 2026.1 English - UG1448

Description

Message HLS 200-448 explicitly informs you about insufficient memory ports allocated for a given array:

WARNING: [HLS 200-448] Lower bound of II is 2 due to multiple operations accessing core:RAM:output_r: operation list {
'store' operation ('output_r_addr_write_ln25', ../srcs/image_roi.cpp:25) of variable 'input_0_load', ../srcs/image_roi.cpp:25 8 bit on array 'output_r', 
'store' operation ('output_r_addr_1_write_ln25', ../srcs/image_roi.cpp:25) of variable 'input_1_load', ../srcs/image_roi.cpp:25 8 bit on array 'output_r', 
'store' operation ('output_r_addr_2_write_ln25', ../srcs/image_roi.cpp:25) of variable 'input_0_load_1', ../srcs/image_roi.cpp:25 8 bit on array 'output_r', 
'store' operation ('output_r_addr_3_write_ln25', ../srcs/image_roi.cpp:25) of variable 'input_1_load_1', ../srcs/image_roi.cpp:25 8 bit on array 'output_r'}

Explanation

In this case, the source code looks like the following. The unroll pragma generates four write accesses to double-ported top output memory output:

    	for (j = 0; j < 1280; ++j) {
#pragma HLS PIPELINE II = 1
#pragma HLS unroll factor=4
			output[j] = input[i*1280 + j];
        }

The Memory Schedule tab in the GUI schedule view for the failing loop highlights this issue by showing four accesses to the output array competing for the two ports of the output array.

Figure 1. Memory Schedule Tab

Recommendation

Partitioning output using the following pragma is a way to resolve this issue:

#pragma HLS array_partition cyclic variable=output factor=2

For more information and for a definition of terms, refer to Pipeline II Violations.