Loop Exit Constraints (HLS 200-878) - Loop Exit Constraints (HLS 200-878) - 2026.1 English - UG1448

Description

WARNING: [HLS 200-878] Unable to schedule the loop exit test ('and' operation 1 bit ('and_ln9', ../dut.cpp:9)) in the first pipeline iteration (II = 4 cycles).
Resolution: For help on HLS 200-878 see docs.amd.com/access/sources/dita/topic?Doc_Version=2026.1%20English&url=ug1448-hls-guidance&resourceid=200-878.html
INFO: [HLS 200-2198] Existing conflicting constraints include from 'and' operation 1 bit ('and_ln9', ../dut.cpp:9) to do.cond with distance of -7 (conflict 1 of 2)
INFO: [HLS 200-2198] Existing conflicting constraints include from do.cond to fifo read operation ('in_r_read', ../dut.cpp:7) on port 'in_r' (../dut.cpp:7) with distance of 0 (conflict 2 of 2)
INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 8, Depth = 29, loop 'VITIS_LOOP_5_1'

Explanation

This message is generated if the II constraint is specified and the scheduler is forced to increase the II because the loop exit condition must be scheduled after the first II cycles. The code shows an example in which the computation of the loop exit condition requires eight cycles, because the floating point multiplication and a floating point comparison require eight cycles at the target frequency on the target device.

void top(hls::stream<double> &in, hls::stream<double> &out) {
  double t;
  bool end;
  do {
#pragma HLS pipeline
    t = in.read();
    out.write(t * t / 17.);
    end = t * 24. != 0;
  } while (end); // this is line 11, where the exit condition is computed
}

The scheduler viewer shows a long chain of operations ending with br_ln11 (the line with while(end);), which is the exit operation from the loop and is highlighted in orange in the following figure.

Figure 1. Scheduler Viewer

Recommendation

In this case, #pragma HLS bind_op can be used to force a lower latency implementation for the dmul operation, leading to a timing violation.

      end = t * 24. != 0;
  #pragma HLS bind_op variable=end op=dmul latency=2

Alternatively, the II can be specified using #pragma HLS pipeline II=N , forcing the selection of a multiplier and a comparator with lower latency, also leading to a timing violation.

For more information and for a definition of terms, refer to Pipeline II Violations.