Input-Output Synchronization Constraints (HLS 200-2253) - Input-Output Synchronization Constraints (HLS 200-2253) - 2026.1 English - UG1448

Description

INFO: [HLS 200-2253] Unable to schedule 'store' operation ('inout_r_addr_write_ln3', dut.cpp:3) of variable 'bitcast_ln3_1', dut.cpp:3 64 bit on array 'inout_r' in the first 4 clock cycle(s).
INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 6, loop 'VITIS_LOOP_2_1'

Explanation

This message is generated if the II constraint is specified and the scheduler is forced to increase the II because some inout accesses must be scheduled after the first II cycles:

void top(int i, double in, double inout[8]) {
#pragma HLS pipeline
#pragma HLS dependence inter false variable=inout
    inout[i] *= in;
}

The multiplication forces the write to inout[i] to be in the sixth cycle of the pipeline. Because all its accesses are forced to be in the first II, this leads to the II=6 for the top function.

Recommendation

In this case, the available options are as follows:

• Specify the II, or use #pragma HLS bind_op to force the scheduler to use a multiplier with smaller latency, possibly leading to a timing violation post-implementation:

  #pragma HLS bind_op latency=…

• If applicable, use #pragma HLS stable to relax the constraint on scheduling the accesses to the input variable a after the first II:

  #pragma HLS stable variable=a

  This option is valid if you can ensure that the variable is not changed before ap_done, for the following reasons:
  • dut is not a dataflow process.
  • It is called in a sequential FSM context, or it is the top function and it does not receive ap_start again until it has generated ap_ready.

For more information and for a definition of terms, refer to Pipeline II Violations.