Description
Warning: [HLS 200-1972] Disabling free running
pipeline (frp) architecture on pipeline 'LOOP_PROCESS' in module
'process_Pipeline_LOOP_PROCESS', because it has M_AXI or AXILite port: a.
Explanation
The pipelined loop is accessing a MAXI interface port and this is not supported.
- Solution 1 (recommended): Buffering the data to an internal FIFO channel
before or after data has been processed inside the pipelined loop. Note: The data processing pipeline should now use the FIFO internal port instead of the MAXI port.
- Solution 2: Try to use the AXIS/AP_HS/FIFO interface port instead.
Example
void process(int a[N], int b[N])
{
LOOP_PROCESS : for ( int i=0; i<N; i++)
#pragma HLS pipeline ii=2 style=frp
b[i] = a[i] + i;
}
void DUT(int a[N], int b[N])
{
#pragma HLS dataflow
#pragma HLS INTERFACE m_axi port=a
#pragma HLS INTERFACE m_axi port=b
int buf[N];
process(a, buf);
...
}