Description
Warning: [HLS 200-1965] Disabling free
running pipeline (frp) architecture on pipeline 'VITIS_LOOP_11_2' in module
'COM_Pipeline_VITIS_LOOP_11_2', because it has II equal to pipeline depth (will fall back to
a sequential design).
Explanation
In this example, the pipelined loop's II is the same as its depth (2), meaning the loop is sequential. Applying FRP to this loop will not help.
Example
void COM(int a[SIZE])
{
int i,j,temp;
for(i = 0; i < SIZE-1; i++)
{
for(j = 0; j < SIZE-1-i; j++)
{
#pragma HLS pipeline style=frp
if(a[j] < a[j+1])
{
temp = a[j+1];
a[j+1] = a[j];
a[j] = temp;
}
}
}
for(i = 0; i < SIZE; i++)
printf("%d\n",a[i]);
}