Description
Warning: [HLS 200-1960] Disabling free running
pipeline (frp) architecture on pipeline 'LOOP_ADD' in module 'mode_add', because it
has AXIS/AP_HS/FIFO read after the first II from a top-level input port.
Explanation
Multiple reads to AXIS/ap_hs/FIFO are seen inside the pipeline, resulting in conflicts across
pipeline stages that prevents FRP from being applied to the pipeline. As a potential
workaround, try to increment the pipeline II to make sure the read occurs at the
first II stage, e.g. #pragma HLS pipeline style=frp II=2
void mode_add(config_t &cfg, hls::stream<int> &in_st, hls::stream<int> &out_st)
{
int total = 0;
LOOP_ADD : for (int i = 0; i < cfg.length; i++) {
#pragma HLS LATENCY min=5 max=5
#pragma HLS pipeline style=frp
total += in_st.read();
out_st << total;
}
}