Array partitioning and array reshaping are commonly used mechanisms to enable parallel access to on-chip memories. The following section discusses array partitioning. Reshaping can be more resource effective when the word size of the original array is much smaller than the word size of a block RAM or UltraRAM. For information about the trade-offs involved, refer to pragma HLS array_partition and pragma HLS array_reshape in the Vitis High-Level Synthesis User Guide (UG1399).
Assume that you need to read (or write) locations i and i+1 of an array in a given pipeline
iteration, and you want to use a single-port memory. Partitioning the memory into two,
one part containing odd addresses and one part containing even addresses, can ensure
that two reads are performed in one cycle. Vitis HLS can
resolve accesses to different banks only if the distance between two accesses is a
constant within a given iteration, as in the previous example.
A[i] and A[i+3] are also disambiguated correctly, while A[i] and A[j+1] are not, even in the
presence of assert(i==j), because the resolution
mechanism cannot reason about different index variables. To ensure that different
partitions are used correctly, make sure that they all use a single index variable.