The TDD control block register map is listed in the following table.
| Address | Description |
|---|---|
0x0
|
DAC TDD mode pin, bit n: DAC channel n |
0x4
|
ADC TDD mode pin, bit n: ADC channel n |
0x8
|
Bit 0: reset, others: reserved |
0xC
|
Bit 0 to 3: ADC hw_trigger_en control |
0x10
|
Symbol to trigger on |
0x14
|
Frame to trigger on |
0x18
|
Arm the trigger |
0x30
|
Tile 0 trigger delay |
0x34
|
Tile 1 trigger delay |
0x38
|
Tile 2 trigger delay |
0x3C
|
Tile 3 trigger delay |
0x44
|
Slot length (unused) |
0x48
|
Guard band length |
0x4C
|
Symbol length |
0x50
|
Symbol type |