A DDR4 memory controller (see
UltraScale
Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide
(PG150)) is instantiated to control the external DDR4 memory. It connects
to an AXI DMA controller (see
AXI DMA LogiCORE IP Product Guide (PG021)). The waveform
loaded into the DDR4 memory is then broadcast to the RF-DAC tiles selected by the AXI
GPIO (see
AXI GPIO LogiCORE IP Product Guide (PG144)). The GPIO connects to
the user_select input of the block RAM generation and
effectively bypasses this block when user_select is
High.
For crossing clock domains, the broadcasting is done in two steps. The first step is part of the DDR clock domain and the second step is part of the RF-DAC tile clock domain. The RF-DAC DDR block architecture is illustrated in the following figure.