A DDR4 memory controller (see UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)) is instantiated to control the external DDR4 memory. The RF-ADC output is duplicated on the output of the RF analyzer block RAM capture block. An AXI4-Stream interconnect is then used as a switch to select which RF-ADC waveform is fed into the DMA and captured into the DDR memory. To allow the software to control the DMA accurately, a TLAST block is created. This block generates a TLAST pulse so that the DMA generates an interrupt after the correct number of samples. Because the dual RF-ADC tiles have two AXI4-Stream outputs in I/Q mode, an AXI4-Stream combiner is used to write both streams in the DDR memory. Consequently, the real mode cannot be used to capture the dual RF-ADC tiles in the DDR. The RF-ADC DDR block architecture is shown in the following figures.
Figure 1. RF-ADC DDR Block Architecture for Quad RF-ADC Tiles
Figure 2. RF-ADC DDR Block Architecture for Dual RF-ADC Tiles
