To communicate between the host and the design, a simple but robust protocol is used. This protocol is a string-based, space-separated command and response protocol. The state machine is represented in the following figure.
Each command is sent in text (ASCII) format, parsed to check that the command is
known and the number of arguments is correct, and then executed. The design returns the
command name plus some parameters or the error type without any parameter if an error
condition occurs. The host can get information on the error by using the getlog command, which reads the metal log buffer (see
Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP
Product Guide (PG269)).
The command can be split into these categories.
- RFDC commands are usually a direct translation of the RFDC driver with an addition of error checking when necessary
- PL design commands control the PL side of the design (MMCM, GPIO, capture and generation memories, etc.)
- Board control commands control some of the board components such as external clocks