Clocking Scheme

Zynq UltraScale+ RFSoC ZCU208 and ZCU216 RF Data Converter Evaluation Tool User Guide (UG1433)

Document ID
UG1433
Release Date
2024-09-26
Revision
1.4 English

The clocking scheme is built to support both individual tile clocks and independent RF-ADC or RF-DAC multi-tile synchronization (MTS). Consequently, two of the typical clocking schemes from the Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) are merged. The first clocking scheme uses the output of each tile to connect to a mixed-mode clock manager (MMCM) or phase-locked loop (PLL), which gives an independent clock per tile. The second clocking scheme supports MTS, takes its input from a fabric pin, and generates an output for the tiles selected by the MTS functions. BUFGMUX and MMCM dual input allows merging these two clocking schemes. For the RF-ADC, a mixture of MMCM and PLL are used. The RF-ADC clocking scheme figure shows a representation for two tiles. The RF-DAC clocking scheme figure shows a representation for two tiles. For the RF-DAC, only the MMCM is used. The path used in the MTS case is shown in red.

Figure 1. RF-ADC Clocking Scheme
Figure 2. RF-DAC Clocking Scheme