The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 09/13/2024 Version 1.3 | |
| JTAG | Updated to correct 2-pole DIP SW3[1:2] setting. |
| 06/09/2023 Version 1.2 | |
| Switches | Removed QSPI32 and revised default value for callout 16. |
| I/O Voltage Rails | Revised voltage for PMC MIO 500, PMC MIO 501, and LP MIO 502. |
| PMC MIO[26:36, 51] Bank 501: Secure Digital (SD) Card IF (J302) | Revised voltage for device bank 501 VCCO from 3.3V to 1.8V. |
| JTAG Chain | Revised figure. |
| Power and Status LEDs | Revised description for DS2. |
| 03/07/2022 Version 1.1 | |
| Models of Boards | Added kit model EK-VMK180-G. |
| Versal Adaptive SoC Kit Numbering | Modified ED option. |
| Board Features and Block Diagram | Clarified 72-bit (64-bit, and 8-bit ECC) DDR4 feature and updated the block diagram accordingly. |
| 01/07/2021 Version 1.0 | |
| Initial release. | N/A |