Reserved Memory - 2025.2 English - UG1400

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
UG1400
Release Date
2025-11-20
Version
2025.2 English

The hardware and software programming environment defines reserved memory, especially for memory containing interrupt vector locations and operating system level routines. The following table lists the reserved memory locations for MicroBlaze, MicroBlaze V, and Arm processors as defined by the processor hardware. For more information on these memory locations, refer to the corresponding processor reference manuals.

For information about the Arm Cortex A9 memory map, refer to the Zynq 7000 SoC Technical Reference Manual (UG585). For the Cortex-R5F, Cortex-A53, and Cortex-A72 memory map, refer to the Zynq UltraScale+ Device Technical Reference Manual (UG1085).

Note: In addition to these memories reserved for hardware use, your software environment can reserve other memories. Refer to the manual of the particular software platform for more details.
Table 1. Hardware Reserved Memory Locations
Processor Family Reserved Memories Reserved Purpose Default Text Start Address
MicroBlaze and MicroBlazeâ„¢ -V 0x0 - 0x4F Reset, Interrupt, Exception, and other reserved vector locations. 0x50