FPGA to CPU triggering is one of the most common use cases of cross-triggering in Zynq.
- There are four trigger inputs on FPGA CTI. You can configure the inputs to halt (EDBGRQ) any of the two CPUs. Similarily, the four FPGA CTI trigger outputs can trigger when a CPU halts (DBGACK).
- The FPGA trigger inputs and outputs can connect to ILA cores. When any of the two CPUs halts, an ILA trigger can halt the CPU(s) and the ILA can trigger to capture the signals it is monitoring.
For more details about setting up cross-triggering to the FTM in Vivado Design Suite, refer to the Cross Trigger Design section in Vivado Design Suite Tutorial: Embedded Processor Hardware Design (UG940).