Debugging Zephyr Applications on Microblaze V - 2025.2 English - UG1400

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
UG1400
Release Date
2025-11-20
Version
2025.2 English

The Vitis Unified IDE enables you to debug Zephyr applications that run on MicroBlaze V processors using the User Managed Mode

For more details on User Managed Mode, see User Managed Mode.

The AMD Zephyr repo is available at: https://github.com/Xilinx/zephyr-amd.git

The following tutorial demonstrates how to debug a Zephyr application using the Vitis Unified IDE in user-managed mode.

Setting up the Zephyr Environment

  1. First, follow the official zephyr guide to set up the Zephyr application development environment. See Zephyr Getting Started.
  2. Replace the upstream repo you cloned down in the previous step with the AMD clone.
cd <local path>/zephyrproject/
mv zephyr zephyr.upstream
git clone https://github.com/Xilinx/zephyr-amd.git  -b xlnx_rel_v2025.1 zephyr
west update
west lopper-install

Creating the Hardware Design

Load Vivado and generate the hardware design (XSA) using the MicroBlaze V Design Preset based on Vivado CED, targeting the AC701 board. Alternatively, you can choose to create your own hardware design. For your own design, make sure that the your hardware design is compatible with the current release of the zephyr-amd repository.

Once your design has been finalized and you have exported the XSA file, you can start integrating with Zephyr.

Preset Design Examples

AMD Vivado offers preset design examples for various evaluation boards. Each embedded hardware design offers a subsystem that can be targeted for the real-time and microcontroller configurations. As of now, Zephyr is supported only for the real-time configuration.

The following sections demonstrates how to implement the MicroBlaze V Design Preset CED, targeting the AC701 board.

Generating the System Device Tree

Refer to the AMD Technical Information Portal for the steps to generate a System Device Tree (SDT) using a hardware design XSA. The SDT is mandatory to generate a Zephyr device tree and Kconfig for targeted hardware designs using the west lopper-command.

. /tools/AMD/Vivado/2025.2/settings64.sh
sdtgen sdt.tcl

Setting up the Zephyr Repository

Because each FPGA based hardware design can have different hardware configurations, you need to update the device tree (boards/amd/<board_name>/<board_name>.dts) based on the targeted hardware design. The base address and interrupt IDs can be different from what is configured in the default device tree. You need to either update .dts and kconfigs (soc/xlnx/<board_name>/Kconfig, soc/xlnx/kconfig.defconfig) manually based on the hardware design or use west lopper-command to set it up using lopper. Subsequent sections provide steps for setting up the DTS for a targeted hardware design using west lopper-command.
LOPPER_DTC_FLAGS="-b 0 -@" west lopper-command -p processor_instance_name -s output_dir/system-top.dts -w <local path>/zephyrproject/zephyr

Example Usage

LOPPER_DTC_FLAGS="-b 0 -@" west lopper-command -p microblaze_riscv_0 -s design_1_wrapper/system-top.dts -w ~/zephyrproject/zephyr
Once the lopper-command has been invoked, the Zephyr environment is ready to build kernel tests and applications for the targeted hardware design. Build a sample test by replacing board with your target using the commands below.
cd zephyr
west build -p -b board tests/misc/test_build/
# The executable would be generated in following location
<zephyr repository path>/build/zephyr/zephyr.elf
west build -p -b mbv32 tests/misc/test_build/

Creating The Launch Configuration

Load Vitis Unified Software Platform, 2025.2 version and open a new folder. The folder opens Vitis in User Managed Mode. Create a new launch configuration by right clicking the Explorer view and selecting Edit Launch Configurations and then Add Configuration.

Set the target processor to microblaze_riscv_0 and provide the path to the zephyr.elf application file.

If the application source path has changed or ELF location is not within your workspace, you need to remap the original path of the source file and the destination path of the source code.

Figure 1. Add Path Map

Launch the debug session. The main.c file loads in the debug perspective.

Figure 2. main.c Launching in Debug Perspective