pragma HLS array_stencil - 2024.1 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2024-05-30
Version
2024.1 English

Description

#pragma HLS array_stencil variable=<name > <off>

Use "#pragma HLS array_stencil variable=xxx off" to disable auto stencil on a variable in a loop.

Global Auto Control

config_array_stencil -throughput_driven <off|on>

Code Canonical Forms and Limitations:

  • Stencil optimization can only be applied to the top level.
  • Loop bounds need to be constant for multi-dimensional stencil patterns.
  • The pragma must be located within the loop.
  • The loop where stencil optimization is applied must require a pipeline pragma with II=1.
  • Stencil optimization requires nested loops to be perfect nested loops.
  • The access pattern should have a fixed pattern.
  • The access pattern order must follow the loop order, for example, it must have a loop increment +/- 1.