create_derived_clock - 2024.2 English - UG1399

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2024-11-13
Version
2024.2 English

Description

Create a constraint for a secondary clock used in a #pragma HLS interface s_axilite clock option, relative to the primary clock frequency.

Syntax

create_derived_clock [OPTIONS]

Options

-name
Name of the secondary clock pin.
-multiply_by
Frequency multiplier (default: 1).
-divide_by
Frequency divisor (default: 1).