Running C/RTL Co-Simulation - Running C/RTL Co-Simulation - 2026.1 English - UG1399

Vitis High-Level Synthesis User Guide (UG1399)
Document ID
UG1399
Release Date
2026-06-23
Version
2026.1 English

Make sure the HLS component is active in the Flow Navigator, or click the Component menu to make it the active component in the tool.

When the HLS component is active, the Flow Navigator enables C Simulation, C Synthesis, C/RTL Co‑simulation, Packaging, and Implementation to build and analyze the component.

For C/RTL Co-simulation of the HLS component, click Run beneath the C/RTL COSIMULATION heading in the Flow Navigator.

You must load a test bench or test bench files to run co-simulation on the HLS component. Prior to running co-simulation, you must also configure the HLS component to support C/RTL co-simulation. Configure the design using the following steps.

Important: Co-simulation does not support input test vectors in the C/C++ test bench (for example: std::random_device). Generate random values one time and save it to a file for C/C++ test bench to use during co-simulation.

Configure the Simulator

You can configure the simulator before running simulation using the C/RTL Co-Simulation section of the Config Editor.

Figure 1. HLS Component RTL Co-Simulation Settings

These configuration commands let you specify how the simulation runs. Refer to Co-Simulation Configuration. Some of the settings for C/RTL Co-Simulation include the following:

trace_level
Specifies the level of trace file output written to the sim/Verilog or sim/VHDL directory of the current solution when the simulation executes. Options include:
all
Output all port and signal waveform data being saved to the trace file.
port
Output waveform trace data for the top-level ports only.
port_hier
Output waveform trace data for the complete port hierarchy.
none
Do not output trace data.
random_stall
Applies a randomized stall for each data transmission.
wave_debug
Enables waveform visualization of all processes in the RTL simulation. Only Vivado logic simulator supports this option. Enabling this option launches the Simulator GUI to let you examine dataflow activity in the waveforms generated by simulation. Refer to the Vivado Design Suite User Guide: Logic Simulation (UG900) for more information on that tool.
disable_deadlock_detection
Disables deadlock detection, and opens the Cosim Deadlock Detection in co-simulation.
enable_dataflow_profiling
Enables capturing profile data for display in the Dataflow Viewer.
Dynamic Deadlock Prevention
Prevent deadlocks by enabling automatic FIFO channel size tuning for dataflow profiling during co-simulation.

Run C/RTL Co-Simulation

With the C/RTL Co-simulation setup defined in the config file you are ready to select Run from the Flow Navigator to begin simulation. You can track the progress of simulation in the Output window. The transcript for the synthesis run has the top function name as <component-name>::co_simulation as shown below.

Tip: The simulation run in the Vitis Unified IDE uses the vitis-run --mode hls --cosim command.
Figure 2. HLS Component Running C/RTL Co-Simulation

The reports available after co-simulation include the following.

  • Summary: Reports the command line used and the time stamp on the results.
  • Cosimulation: Displays general information about the design. Displays options that Co-simulation uses, and displays performance and resource estimates for the design hierarchy. If you enable enable_dataflow_profiling, performance data is back annotated to the Dataflow Viewer report. See Dataflow Viewer.
    Important: If you want to calculate II, you must ensure there are at least two transactions in the RTL simulation.
  • Timeline Trace: Refer to Timeline Trace Viewer.
  • Wave Viewer: Refer to Viewing Simulation Waveforms.
  • Function Call Graph: Displays the post Co-simulation call graph. Refer to Function Call Graph.