Running C Synthesis - Running C Synthesis - 2026.1 English - UG1399

Specifying Interface Defaults and General Settings

The HLS component infers default interface ports for top-level arguments based on the syn.interface.default_axi setting. When enabled, the tool infers AXI interfaces (m_axi, s_axilite, or axis) for arguments that do not have an explicit interface pragma.

Figure 1. Initial HLS Settings

You can set syn.interface.default_axi when you create the HLS component, or modify it later in the Config Editor. On the same page, you can also specify the clock target, clock uncertainty, and the package.output.format value.

These selections produce the following entries in the config file.

part=xcvc1902-vsva2197-2MP-e-S

[hls]
package.output.format=xo
package.output.syn=false
clock=4ns
clock_uncertainty=15%
syn.interface.default_axi=1

Loading Source Files and Identifying the Top Function

Generally, you define and load the source code for the HLS component at the time of creation. However, you can bypass that step when creating the component. You need to add the source files prior to synthesizing the design. To add source files to an existing HLS component, follow the steps below.

Figure 2. HLS Component Synthesis Sources

1. Open the HLS component configuration file.
2. Navigate to the C Synthesis sources section in the Config Editor.
3. Review the list of source files currently added to the HLS component.
4. To add new source files:
   1. Select Add item.
   2. In the file browser, navigate to the source files.
   3. Select one or more source files to add to the HLS component.
5. To edit or delete an existing source file:
   1. Select the source file.
   2. Modify or remove the file as needed.

6. To add compilation flags for all source files:

   1. Enter the required flags in Flags common to all files.
   2. Use CFLAGS for synthesis.
   3. Use CSIMFLAGS for simulation.

7. To add or modify compilation flags for a specific source file:

   • Select the source file.
   • Select Edit item.
   • Add or update the file‑specific flags, file name, or path.

8. Specify the top function:

   • Select top.
   • In the Select Top Function dialog, choose the function to use as the top‑level RTL module.
   • Confirm the selection.

[HLS]
syn.file=<path/to/file.cpp>
syn.file_cflags=<path/to/file.cpp>,<cflag>
syn.file_csimflags=<path/to/file.cpp>,<csimflag>
syn.cflags=<cflag for all files>
syn.csimflags=<csimflag for all files>
syn.top=<top function name>

Configuring Default Settings

For the HLS component, the Vitis Unified IDE offers a variety of commands to configure the default settings for synthesis and simulation. These configuration commands are presented in Config Editor under the heading of C Synthesis. See Compile Options, Interface Configuration, and RTL Configuration.

Figure 3. HLS Component Default Settings

Assigning Design Directives

Figure 4. HLS Component Directives

Design directives provide customization for the synthesis results of the source code. Change the directives across multiple synthesis runs to change the results or optimize your design. You can add directives as HLS pragmas directly to the source code. You can also add HLS Optimization Directives to the configuration file to use in an HLS component. In the Config File editor, you can see the various directives. Select Add Item to open the Directive editor.

[HLS]
syn.directive.dataflow=dct
syn.directive.array_partition=dct buf_2d_in type=block factor=4
syn.directive.pipeline=dct2d II=4

Run Synthesis

After you define the key elements of the HLS component in the config file, you are ready to run Synthesis. Click Run from the Flow Navigator to begin Synthesis. You can track the progress of the synthesis run in the Output window. The transcript for the synthesis run has the top function name as <component-name>::synthesis. During the synthesis process messages are transcripted to the console window, and to the vitis_hls.log file.

Figure 5. HLS Component Running Synthesis

After synthesis is complete, see the Reports folder under the Run command. The reports available after synthesis are as follows:

• Summary: Reports the command line used and the time stamp on the results.
• Synthesis: Reports the synthesis results with information on quality of results, HW interfaces, burst transactions and more. Refer to Synthesis Summary for more information.
• Function Call Graph: Displays the HLS component after C Synthesis or C/RTL Co-simulation to show the throughput of the design in terms of latency and II as described in Function Call Graph.
• Schedule Viewer: Shows each operation and control step of the function, and the clock cycle that it executes in, as described in Schedule Viewer.
• Dataflow Viewer: Only available when the DATAFLOW pragma or directive is used in the design. This report shows the dataflow structure inferred by the tool as described in Dataflow Viewer.
• Kernel Guidance: Reports Guidance messages to provide design advice for the source code and synthesis results.