References - 2025.1 English - UG1399

These documents provide supplemental material useful with this guide:

1. UltraScale Architecture DSP Slice (UG579)
2. Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)
3. Vivado Design Suite User Guide: Logic Simulation (UG900)
4. Vivado Design Suite User Guide: Synthesis (UG901)
5. Vivado Design Suite User Guide: Implementation (UG904)
6. Vivado Design Suite Tcl Command Reference Guide (UG835)
7. Introduction to FPGA Design with Vivado High-Level Synthesis (UG998)
8. Vivado Design Suite Tutorial: High-Level Synthesis (UG871)
9. Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
10. Floating-Point Operator LogiCORE IP Product Guide (PG060)
11. Fast Fourier Transform LogiCORE IP Product Guide (PG109)
12. FIR Compiler LogiCORE IP Product Guide (PG149)
13. DDS Compiler LogiCORE IP Product Guide (PG141)
14. Vivado Design Suite: AXI Reference Guide (UG1037)
15. Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)
16. Data Center Acceleration using Vitis (UG1700)
17. Embedded Design Development Using Vitis (UG1701)
18. Vitis Reference Guide (UG1702)
19. Versal Adaptive SoC DSP Engine Architecture Manual (AM004)
20. Floating-Point Design with Vivado HLS (XAPP599)
21. Option Summary page on the GCC website (gcc.gnu.org/onlinedocs/gcc/Option-Summary.html)
22. Accellera website (http://www.accellera.org/)
23. AWGN page on the MathWorks website (http://www.mathworks.com/help/comm/ug/awgn-channel.html)
24. AMD Vivado™ Design Suite Documentation