Packaging the RTL Design - Packaging the RTL Design - 2026.1 English - UG1399

Configure Packaging

You can configure the packaging process to export the IP or kernel according to your settings prior to running package. The Config File Editor separates Packaging into Output and IP sections as shown below.

Specifying the Output Format and Output File

You must specify the output.format for the RTL synthesis results. The default format is RTL, which lets the tool synthesize the Verilog and VHDL code from the C/C++ source files. The default format does not generate the Vivado IP or Vitis kernel as an output product. The approach lets you run synthesis quickly without having to generate hardware files at every iteration. Generate the hardware files to use the RTL design in downstream flows such as embedded software or application projects. The flow you are supporting in your design determines the best choice for output format.

The following are the Package options and their default values.

package.output.file

The tool determines the output file name and location and uses the top function name of the HLS component by default. However, you can specify the name and location to override the default values.

package.output.format

The output.format command supports several different formats as shown in the following table.

Table 1. Package Output Formats

Package Format	Default Location	Comments
package.output.format=ip_catalog	<comp-name>.zip	Export the IP as a ZIP file. You can add the file to the Vivado IP catalog. The impl/ip folder also contains the contents of the unzipped IP.
package.output.format=xo	<comp-name>.xo	You can use the XO file output for linking by the Vitis compiler in the application acceleration development flow. You can link the Vitis kernel with other kernels and the target accelerator card to build the xclbin file for your accelerated application.
package.output.format=rtl	Creates Verilog and VHDL folders in the HLS component working directory.	This option lets you skip the generation of the packaged IP or XO modules to save time while iterating on the initial design.

package.output.syn

Enable or disable the creation of the IP or XO during synthesis. Specify false to disable generation of the packaged IP or XO, or specify true to enable it. This option lets you skip the generation of the packaged IP or XO modules to save time while iterating on the initial design.

[HLS]
package.output.format=xo
package.output.file=../../<filename>
package.output.syn=false

IP Configuration

When you specify package.output.format=ip_catalog in the HLS configuration file, you can also specify additional fields for the IP. These include the vendor, library, name, and version (VLNV) of the IP.

Use the Configuration information to differentiate between multiple instances of the same IP when loading into a Vivado IP catalog. For example, after you package an implementation for the IP catalog, you can create and package a new solution as IP. By default, the new solution inherits the same name and configuration information. If you add the new solution to the IP catalog, the catalog identifies it as an updated version of the same IP. The catalog uses the most recently added version.

See the following for the IP options and their default values.

package.ip.vendor

xilinx.com

package.ip.library

hls

package.ip.name

Default to HLS component name

package.ip.version

1.0

package.ip.description

An IP generated by HLS component

package.ip.display_name

This field left blank

package.ip.taxonomy

This field left blank

package.ip.xdc_file

This field left blank

package.ip.xdc_ooc_file

This field left blank

After packaging, the tool writes the ZIP file archive or XO kernel to the package.output.file location or the HLS component folder. You can export the IP file into the Vivado IP catalog and use it in any design. You can also use the exported Vitis kernel with the v++ --link command as part of a larger system design.

Software Driver Files

For designs that include AXI4-Lite slave interfaces, the tool creates a set of software driver files during export. A Vitis embedded software development project can include these C driver files and use them to access the AXI4-Lite slave port.

The software driver files are writes to the directory solution/impl/ip/drivers. The files are in the packaged IP export.zip. Refer to the AXI4-Lite Interface section for details on the C driver files.