Output of C/RTL Co-Simulation - Output of C/RTL Co-Simulation - 2026.1 English - UG1399

In the Vitis Unified IDE, the hierarchy of the HLS component is <workspace>/<component>/<component>/hls/. Select HLS component in the Vitis Component Explorer and select Open In Terminal from the right-click menu.

When C/RTL Cosimulation completes, go to the sim folder in the solution folder. This folder contains the following elements.

• A verification folder sim/verilog or vhdl for each verified RTL language.
  • The RTL files for simulation are in the verilog or vhdl folder.
  • The RTL simulation executes in the verification folder.
  • Any outputs, such as trace files and waveform files, writes to the verilog or vhdl folder.
• The sim/report folder contains the report and log file for each type of RTL simulated.
• Additional folders sim/autowrap, and tv, wrap and wrap_pc are work folders used by the HLS compiler. There are no user files in these folders.