Description
Op Binding (syn.op / config_op)
Binds arithmetic operations to specific RTL implementations globally.
- Config file syntax: Space-separated key:value pairs (not =).
- Tcl syntax: config_op <operator> -impl <value> [-latency <N>] [-precision [low|high|standard]].
Syntax
| Category | Operators |
|---|---|
| Integer | mul, add, sub |
| Single-precision float | fadd, fsub, fdiv, fmul, fexp, flog, frsqrt, frecip, fsqrt |
| Double-precision float | dadd, dsub, ddiv, dexp, dlog, dmul, drsqrt, drecip, dsqrt |
| Half-precision float | hadd, hsub, hdiv, hmul, hsqrt |
| Accumulator / MAC | facc, fmacc, fmadd |
| `impl` | Default | Description |
|---|---|---|
| all | ✅ (default) | All implementations — tool selects the binding |
| dsp | - | Use DSP resources |
| fabric | - | Use non-DSP resources (LUT fabric |
| meddsp | - | Floating Point IP Medium Usage of DSP resources |
| fulldsp | - | Floating Point IP Full Usage of DSP resources |
| maxdsp | - | Floating Point IP Max Usage of DSP resources |
| primitivedsp | - | Floating Point IP Primitive Usage of DSP resources |
| auto | - | Enable inference of combined facc | fmacc | fmadd operators |
| none | - | Disable inference of combined facc | fmacc | fmadd operators |
Tip: Comparison operators (such as
dcmp) are implemented in LUTs and cannot be implemented outside of the fabric or
mapped to DSPs, and so are not configurable with config_op
or bind_op.
| `precision` | Default | Description |
|---|---|---|
| standard | ✅ (default) | Standard floating-point accumulation and multiply-add. Always uses a true floating-point accumulator, pipelined with II=1 on AMD Versal™ , II of 3–5 on non-AMD Versal™ . |
| low | - | Low precision (60-bit and 100-bit integer) accumulation. Only available on certain non-Versal devices. May cause RTL/Co-Sim mismatches. Can always be pipelined with II=1, but uses ~3x resources of standard. |
| fabric | - | High precision (one extra bit) fused multiply-add. Useful for high-precision applications, efficient on Versal. May cause RTL/Co-Sim mismatches due to extra precision. Uses more resources than standard. |
Defaults
config_op defaults: impl=all, latency=-1 (no constraint), precision=standard.Tip: The latency can be specified for
a specific operation without specifying the implementation (-impl). This leaves
Vitis HLS to choose the implementation while managing the latency.
Config File Usage
ini
[hls]
syn.op=op:mul impl:dsp latency:3
syn.op=op:fadd impl:fulldsp
syn.op=op:fmul impl:maxdsp latency:5
Tcl Usage
tcl
config_op mul -impl dsp -latency 3
config_op fadd -impl fulldsp
config_op fmacc -impl dsp -precision standard
Examples
tcl
# Bind the addition operation to fabric with a specified latency:
config_op add -impl fabric -latency 2
# Enable floating-point accumulator with low-precision for II=1 on non-Versal:
config_op facc -impl auto -precision low