Mapping Direct I/O Streams to SAXI Lite Interface - 2025.2 English - UG1399

The Vitis HLS tool provides the capability to map Direct I/O streams, often used for simpler data transfers or control signals, directly onto a standard SAXI Lite interface for communication with the processor or other IP cores. The following procedure outlines how to configure this mapping:

1. Choose the port protocol to be associated with the SAXI Lite interface.
2. Add the SAXI Lite interface pragma.
3. Use the read/write methods.

void sub_task1(hls::stream<int>& in, hls::stream<int>& out) {
    int c = in.read();
    out.write(c + 2);
}

void sub_task2(hls::stream<int>& in, hls::stream<int>& out) {
    int c = in.read();
    out.write(c - 2);
}

void task2(hls::stream<int>& in, hls::stream<int>& out, hls::ap_none<int> &n) {
    int c = in.read();
    int var = n.read();
    out.write(c + var);
}

void test(hls::stream<int>& in, hls::stream<int>& out, hls::ap_none<int> &bias) {
#pragma HLS interface s_axilite port=bias
    HLS_TASK_STREAM<int> s1;
    HLS_TASK_STREAM<int> s2;
    HLS_TASK t(task2, s2, out, bias);
    HLS_TASK t1(sub_task1, in, s1);
    HLS_TASK t2(sub_task2, s1, s2);
}