M_AXI Channels - 2025.1 English - UG1399

Vitis High-Level Synthesis User Guide (UG1399)
Document ID
UG1399
Release Date
2025-05-29
Version
2025.1 English

M_AXI channels implement a separate channel for each pointer argument mapped to a single AXI interface, rather than requiring a separate adapter.

Figure 1. Maxi Adapter

This enables the following benefits:

  • The kernel uses fewer M_AXI adapters and consumes fewer hardware resources.
  • Multiple pointer arguments mapped to a single AXI interface can be used inside a dataflow region.
  • Using a unique AXI ID for each pointer argument enables burst interleaving which can result in higher utilization of the AXI bus bandwidth.

There are two methods to enable this feature in your design:

  • Enable globally on m_axi interfaces using the syn.interface.m_axi_auto_id_channel=true configuration command as described in Interface Configuration. The HLS tool automatically adds channels to the m_axi adapter when this is enabled.
  • Enable on a specific m_axi interface using the channel option of the INTERFACE pragma or directive as described in syn.directive.interface.

From the architectural viewpoint, each MAXI bundle is split into two parts:

  • One load and/or store unit (LSU) per channel and per direction (For example, if an input pointer and an output pointer have the same channel ID, you get one load unit and one store unit).
    • If you do not use the channel option, there is just one load unit and one store unit for all the MAXI top pointers mapped to that bundle.
    • The LSU contains the cache, if enabled. The picture refers to LSUs with the cache. If there is no cache, then there is no tag mem and no valid mem, of course.
    • If multiple top pointers are mapped to the same channel (or to the default single channel), they must all have the same cache config, or no cache.
    • The LSU contains the data and address buffers that enable as many kernel-side bursts to be executed as required by the burst length and number of pending requests configured by the user or auto-inferred by the FE. It is the most BRAM-intensive part of the adapter.
    • Each LSU has its own AXI ID, hence different LSUs could generate interleaved bursts, hence more channels imply better overall throughput if multiple top pointers mapped to the same bundle are accessed concurrently by the kernel.
  • One read adapter and one write adapter.
    • The adapters do not buffer the data but buffer the pending requests until the responses return.
    • They break the potentially very long bursts generated by the kernel into chunks that satisfy the AXI-mandated burst length restrictions.