Description
Interface (`syn.interface.*` / `config_interface`)
Sets global defaults for AXI and port interface behavior.
Syntax
| Option | Config File | Tcl | Default | Type/Values | Description |
|---|---|---|---|---|---|
| clock_enable | syn.interface.clock_enable=true | config_interface -clock_enable | 0 | bool | Add a clock enable (ce) port to the top-level block. |
| default_slave_interface | syn.interface.default_slave_interface=[s_axilite|none] | config_interface -default_slave_interface [s_axilite|none] | s_axilite | enum | Default interface type for scalar top-level ports. |
| m_axi_addr64 | syn.interface.m_axi_addr64=true | config_interface -m_axi_addr64 | 1 | bool | Use 64-bit addresses on all M_AXI interfaces. |
| m_axi_alignment_byte_size | syn.interface.m_axi_alignment_byte_size=<N> | config_interface -m_axi_alignment_byte_size <N> | 1 | int | M_AXI address alignment requirement in bytes. |
| m_axi_alignment_size | syn.interface.m_axi_alignment_size=<N> | config_interface -m_axi_alignment_size <N> | 0 | int | M_AXI alignment size in elements (distinct from m_axi_alignment_byte_size). |
| m_axi_auto_id_channel | syn.interface.m_axi_auto_id_channel=true | config_interface -m_axi_auto_id_channel | 0 | bool | Automatically assign unique ID channels to M_AXI interfaces. |
| m_axi_auto_max_ports | syn.interface.m_axi_auto_max_ports=true | config_interface -m_axi_auto_max_ports | 0 | bool | Automatically maximize the number of M_AXI ports for best performance. |
| m_axi_buffer_impl | syn.interface.m_axi_buffer_impl=[bram|lutram|uram|auto] | config_interface -m_axi_buffer_impl [bram|lutram|uram|auto] | bram | enum | Implementation resource for M_AXI internal buffers. |
| m_axi_cache_impl | syn.interface.m_axi_cache_impl=[auto|lutram|bram|uram] | config_interface -m_axi_cache_impl [auto|lutram|bram|uram] | auto | enum | Implementation resource for M_AXI cache (when using #pragma HLS cache). |
| m_axi_conservative_mode | syn.interface.m_axi_conservative_mode=<bool> | config_interface -m_axi_conservative_mode <bool> | 1 | bool | Enable conservative mode for M_AXI — reduces pipelining across burst boundaries. |
| m_axi_flush_mode | syn.interface.m_axi_flush_mode=true | config_interface -m_axi_flush_mode | 0 | bool | Enable flush mode for M_AXI write channels. |
| m_axi_latency | syn.interface.m_axi_latency=<N> | config_interface -m_axi_latency <N> | 0 | int | Assumed M_AXI bus latency in clock cycles (used for scheduling). |
| m_axi_max_bitwidth | syn.interface.m_axi_max_bitwidth=<N> | config_interface -m_axi_max_bitwidth <N> | 1024 | int | Maximum bus width in bits for all M_AXI interfaces. |
| m_axi_max_read_burst_length | syn.interface.m_axi_max_read_burst_length=<N> | config_interface -m_axi_max_read_burst_length <N> | 16 | int | Maximum read burst length for M_AXI interfaces. |
| m_axi_max_widen_bitwidth | syn.interface.m_axi_max_widen_bitwidth=<N> | config_interface -m_axi_max_widen_bitwidth <N> | 0 | int | Assumed M_AXI bus latency in clock cycles (used for scheduling). |
| m_axi_max_write_burst_length | syn.interface.m_axi_max_bitwidth=<N> | config_interface -m_axi_max_bitwidth <N> | 1024 | int | Maximum bus width in bits for all M_AXI interfaces. |
| m_axi_min_bitwidth | syn.interface.m_axi_max_read_burst_length=<N> | config_interface -m_axi_max_read_burst_length <N> | 16 | int | Maximum read burst length for M_AXI interfaces. |
| m_axi_num_read_outstanding | syn.interface.m_axi_max_widen_bitwidth=<N> | config_interface -m_axi_max_widen_bitwidth <N> | 0 | int | Maximum bit width the tool may widen M_AXI data buses to. 0 = disabled. |
| m_axi_num_write_outstanding | syn.interface.m_axi_max_write_burst_length=<N> | config_interface -m_axi_max_write_burst_length <N> | 16 | int | Maximum write burst length for M_AXI interfaces. |
| m_axi_offset | syn.interface.m_axi_offset=[off|slave|direct] | config_interface -m_axi_offset [off|slave|direct] | slave | enum | M_AXI base address offset mode: off = no offset, slave = via AXI-Lite register, direct = dedicated port. |
| register_io | syn.interface.register_io=[off|scalar_in|scalar_out|scalar_all] | config_interface -register_io [off|scalar_in|scalar_out|scalar_all] | off | enum | Add mailbox register(s) to S_AXILite interface for software-hardware communication. |
| s_axilite_data64 | syn.interface.s_axilite_data64=true | config_interface -s_axilite_data64 | 0 | bool | Use 64-bit data width for S_AXILite interfaces. |
| s_axilite_interrupt_mode | syn.interface.s_axilite_interrupt_mode=[cor|tow] | config_interface -s_axilite_interrupt_mode [cor|tow] | tow | enum | Interrupt register mode: cor (clear-on-read) or tow (toggle-on-write). |
| s_axilite_mailbox | syn.interface.s_axilite_mailbox=[in|out|both|none] | config_interface -s_axilite_mailbox [in|out|both|none] | none | enum | Add mailbox register(s) to S_AXILite interface for software-hardware communication. |
| s_axilite_memory_auto_widen | syn.interface.s_axilite_memory_auto_widen=<bool> | config_interface -s_axilite_memory_auto_widen <bool> | true | bool | Automatically widen S_AXILite memory-mapped registers to improve access efficiency. |
| s_axilite_status_regs | syn.interface.s_axilite_status_regs=[ecc|off] | config_interface -s_axilite_status_regs [ecc|off] | off | enum | Add ECC status registers to S_AXILite interface. |
| s_axilite_sw_reset | syn.interface.s_axilite_sw_reset=true | config_interface -s_axilite_sw_reset | 0 | bool | Add a software-controlled reset register to S_AXILite interface. |
Usage
ini
[hls]
syn.interface.m_axi_latency=64
syn.interface.m_axi_max_read_burst_length=256
syn.interface.m_axi_max_write_burst_length=256
syn.interface.m_axi_num_read_outstanding=16
syn.interface.m_axi_num_write_outstanding=16
syn.interface.m_axi_offset=slave
syn.interface.register_io=scalar_all
syn.interface.default_slave_interface=s_axilite
tcl
config_interface \
-m_axi_latency 64 \
-m_axi_max_read_burst_length 256 \
-m_axi_max_write_burst_length 256 \
-m_axi_num_read_outstanding 16 \
-m_axi_num_write_outstanding 16 \
-m_axi_offset slave \
-register_io scalar_all \
-default_slave_interface s_axilite