DSP Intrinsics - 2024.2 English - UG1399

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2024-11-13
Version
2024.2 English

Integer arithmetic is automatically mapped to DSP resources by the VHLS compiler, however, an experienced designer, familiar with the internal architecture of the DSP48E1, DSP48E2 or DSP58 units, can now use DSP intrinsic functions to create DSP instances with:

  • A user-specified opcode via an intrinsic function name, e.g. add_mul_add or mul_add (note those are contained in specific namespaces detailed later).
  • A given set of registers via a template argument of the intrinsic that encodes the DSP register names as a set of values OR-ed together to get multiple registers.
  • A given use of DSP cascading ports, if allowed by the underlying placement tool.

By including hls_dsp_builtins.h and using the functions and classes described below.

There is currently no support for simple add and mul operations mapped to a DSP, because regular automated DSP inferencing and latency specification, via bind_op, works well in those cases.