Creating an AXI4 Interface with 32-bit Address - Creating an AXI4 Interface with 32-bit Address - 2026.1 English - UG1399

By default, Vitis HLS implements the AXI4 port with a 64-bit address bus. However, some devices such as the AMD Zynq™ 7000 have a 32 bit address bus. In this case you can implement the AXI4 interface with a 32-bit address bus by setting the syn.interface.m_axi_addr64=0 configuration command to disable the 64-bit address bus. Vitis HLS