Co-simulation - Co-simulation - 2026.1 English - UG1399

Vitis High-Level Synthesis User Guide (UG1399)
Document ID
UG1399
Release Date
2026-06-23
Version
2026.1 English

Description

C Simulation (csim.* / config_csim)Co-simulation (cosim.* / config_cosim).

Controls RTL co-simulation execution. Settings live in the [hls] config file; the Tcl equivalent is config_cosim (persistent configuration) or passing arguments directly to cosim_design (per-run).

Syntax

Table 1. Configuration Table
Option Config File Tcl Default Type Description
O cosim.O=true -O — bool Enable compiler optimizations during co-simulation (faster simulation).
argv cosim.argv=<string> -argv <string> — string Command-line arguments passed to the test bench main().
compiled_library_dir cosim.compiled_library_dir=<path> -compiled_library_dir <path> — bool Path to pre-compiled simulation library directory.
coverage cosim.coverage=true -coverage 0 bool Enable code coverage collection during co-simulation.
disable_binary_tv cosim.disable_binary_tv=true -disable_binary_tv — bool Disable binary test vectors; use ASCII instead.
disable_deadlock_detection cosim.disable_deadlock_detection=true -disable_deadlock_detection — bool Disable deadlock detection during co-simulation.
disable_dependency_check cosim.disable_dependency_check=true -disable_dependency_check — bool Disable inter-transaction dependency checking.
enable_changing_stable_inputs (via `cosim_design` Tcl command) cosim_design -enable_changing_stable_inputs — bool Allow stable inputs to change between transactions during co-simulation. Mentioned in cosim_design Tcl command reference.
enable_dataflow_profiling cosim.enable_dataflow_profiling=true -enable_dataflow_profiling — bool Enable dataflow channel profiling (FIFO depths, stall cycles).
enable_fifo_sizing cosim.enable_fifo_sizing=true -enable_fifo_sizing — bool Enable automatic FIFO depth sizing based on co-simulation profiling.
enable_tasks_with_m_axi cosim.enable_tasks_with_m_axi=true -enable_tasks_with_m_axi — bool Enable co-simulation of designs using M_AXI with dataflow tasks.
hwemu_trace_dir cosim.hwemu_trace_dir=<path> -hwemu_trace_dir <path> — string Directory for hardware emulation trace files.
ldflags cosim.ldflags=<flags> -ldflags <flags> — string Linker flags for co-simulation.
mflags cosim.mflags=<flags> -mflags <flags> — string Additional make flags for co-simulation build.
random_stall cosim.random_stall=true -random_stall — bool Insert random stalls in AXI interfaces to stress test backpressure handling.
rtl cosim.rtl=[verilog|vhdl|systemc] -rtl [verilog|vhdl|systemc] verilog enum RTL language to use for co-simulation.
setup cosim.setup=true -setup — bool Only set up the cosim environment; do not run simulation.
stable_axilite_update cosim.stable_axilite_update=true -stable_axilite_update — bool Assume AXI4-Lite slave registers are stable after write (no re-read needed).
tool cosim.tool=[xsim|modelsim|questa|riviera|vcssimulator|xcelium] -tool [xsim|...] xsim enum RTL simulator tool to use.
trace_level cosim.trace_level=[none|all|port|port_hier] -trace_level [none|all|port|port_hier] none enum Waveform trace detail level: none = no trace data saved (default); all = all port and signal waveforms; port = top-level ports only; port_hier = all ports in the design hierarchy. Trace file is saved in sim/Verilog or sim/VHDL.
user_stall cosim.user_stall=<val> `-user_stall <val>` — string User-specified stall specification for AXI interfaces.
wave_debug cosim.wave_debug=true `-wave_debug` — bool Enable waveform generation for post-simulation debug.

Usage



ini
[hls]
cosim.O=true
cosim.trace_level=all
cosim.enable_dataflow_profiling=true
cosim.tool=xsim
cosim.rtl=verilog

tcl
config_cosim -O -trace_level all -enable_dataflow_profiling -tool xsim -rtl verilog
cosim_design