AXI4-Stream Interfaces with Side-Channels - AXI4-Stream Interfaces with Side-Channels - 2026.1 English - UG1399

The following two example show how the side-channels can be used directly in the C/C++ code and implemented on the interface. The code uses #include "ap_axi_sdata.h" to provide an API to handle the side-channels of the AXI4-Stream interface.

The first example uses recommended APIs with getters/setters listed below while the second example uses the legacy coding style.

Table for getters/setters APIs:
Getters	Setters
get_data()	set_data()
get_keep()	set_keep()
get_strb()	set_strb()
get_user()	set_user()
get_last()	set_last()
get_id()	set_id()
get_dest()	set_dest()


First example:
#include "ap_axi_sdata.h"
#include "ap_int.h"
#include "hls_stream.h"

#define DWIDTH 32
typedef ap_axiu<DWIDTH, 1, 1, 1> trans_pkt;

extern "C"
{
    void krnl_stream_vmult(hls::stream<trans_pkt> &A,
                           hls::stream<trans_pkt> &B)
    {
#pragma HLS INTERFACE mode = axis port = A
#pragma HLS INTERFACE mode = axis port = B
#pragma HLS INTERFACE mode = s_axilite port = return bundle = control
        bool eos = false;
    vmult: do
        {
#pragma HLS PIPELINE II = 1
            trans_pkt t2 = A.read();
            
            // Packet for Output
            trans_pkt t_out;
            
            // Reading data from input packet
            ap_uint<DWIDTH> in2 = t2.get_data();
            ap_uint<DWIDTH> tmpOut = in2 * 5;

            // Setting data and configuration to output packet
            t_out.set_data(tmpOut);
            t_out.set_last(t2.get_last());
            t_out.set_keep(-1); // Enabling all bytes
            // Writing packet to output stream
            B.write(t_out);
            if (t2.get_last())
            {
                eos = true;
            }
        } while (eos == false);
    }
}

The second example with legacy coding style:

#include "ap_axi_sdata.h"
#include "ap_int.h"
#include "hls_stream.h"

#define DWIDTH 32

typedef ap_axiu<DWIDTH, 1, 1, 1> trans_pkt;

extern "C"{
    void krnl_stream_vmult(hls::stream<trans_pkt> &A, 
						   hls::stream<trans_pkt> &B) {
#pragma HLS INTERFACE mode=axis port=A
#pragma HLS INTERFACE mode=axis port=B
#pragma HLS INTERFACE mode=s_axilite port=return bundle=control
        bool eos = false;
        
        vmult: do {
#pragma HLS PIPELINE II=1
            trans_pkt t2 = A.read();
            
            // Packet for Output
            trans_pkt t_out;
            
            // Reading data from input packet
            ap_uint<DWIDTH> in2 = t2.data;
            ap_uint<DWIDTH> tmpOut = in2 * 5;

            // Setting data and configuration to output packet
            t_out.data = tmpOut;
            t_out.last = t2.last;
            t_out.keep = -1; //Enabling all bytes
            // Writing packet to output stream
            B.write(t_out);
            if (t2.last) {
               eos = true;
            }
        } while (eos == false);
    }
}

After synthesis, both the A and B arguments are implemented with data ports, the standard AXI4-Stream protocol ports, TVALID and TREADY and all of the optional ports described in the struct.