Syncing PL Clocks with the AI Engine - 2024.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2024-05-30
Version
2024.1 English

In the ADF programming model, a PLIO represents an AXI4-Stream attachment point from the AI Engine to a PL component (either a PL kernel or a platform IP). PLIO clock frequencies can be specified explicitly to match the PL interfaces in simulation. In addition, when you link the ADF graph into the platform using the v++ -link command, you can direct the tools to generate precisely the clock frequencies required by your application. PL kernels can be independently clocked, and the v++ linker will automatically insert clock domain crossing circuitry into the design as needed.

The recommended best practice to sync AI Engine clocks with PL is as follows:

  1. If you know the PLIO clock frequencies, they should be specified in the ADF graph PLIO constructors. If every PLIO will be clocked at the same frequency, instead of specifying in constructors, use v++ -c --mode aie --freqhz <frequency>.

    If PLIO clock frequencies are not known at ADF graph compilation time, defer the actual binding until v++ link time and the compiler will assume all are clocked at 100 MHz for simulation.

  2. For the Vitis compilation of a PL kernel peer of a PLIO, specify the same clock frequency.
    v++ -c --mode hls -freqhz <frequency>
  3. When linking the compiled ADF graph (libadf.a) with the compiled .xo PL kernels, specify the same PL frequencies. If needed, the link-time clock frequencies can override compile time frequencies. In respect to PLIOs, AI Engine simulation behavior can differ from hardware.
    v++ -l --platform <pfm_name> --freqhz <frequency>