Platform Clock Setting - 2024.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2024.1 English

When setting the clock for the Vitis Platform, you can set the clock according to the following rules.

  • Use MBUFGCE along with HARDSYNC when generating higher clock frequencies to enable lower clock skew.
    Figure 1. Output Clocks
  • Clocks which are MBUFGCE cannot be used as ref clocks for clock generation.
  • For the VCK190 base platform for 2024.1, using corresponding to 625, 312.5, 156.25, 78.125 MHz can no longer be used as ref clocks and should be updated to use another or --frezhq per design requirements. In the example design below, 625 MHz is generated by clk_out3 and clk_out4_o1_o1 as shown in following figure. If you want to use 625 MHz as a reference clock, you must use clk_out3. Clock clk_out3 is the base clock originating from MMCM using BUFG, whereas clock_out4_o1_o1 is also originating from MMCM but using MBUFGCE. In MBUFGCE, the actual division takes place in the leaf cells, and cannot be routed back as reference input to the inferred new MMCM (clock wizard).

    Figure 2. Platform Setup

  • PFM.CLK status attribute value fixed_non_ref enables platform use of MBUFGCE clocks.
    • Set status = fixed_non_ref in the Clock tab setting in Platform Setup.
    • For fixed_non_ref clocks, use clock as provided by the base platform denoted by
    • For fixed clocks, use clock as provided by the base platform denoted by; alternatively, if required, use as a reference to an inferred clock wizard to generate the required clock frequency. Inferred clocks can occur if there are clock domain conversions or data width changes.