Flow Guidelines and Limitations - 2024.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2024-05-30
Version
2024.1 English

The v++ compiler operates on a Vivado project that has been encapsulated in an extensible XSA built in Vivado. Conversely, the block design of the VMA is imported into a project as a design source that the user can continue to modify in Vivado.

The following are supported operations:

  • Adding, removing, and reconfiguring IPs and RTL modules outside of and unconnected to the Vitis region hierarchy within/outside the dynamic region block design.
  • Add, removing, or changing connections unconnected to the Vitis region hierarchy within/outside the dynamic region block design.
  • Changing clock frequencies on clock wizard instances outside of the Vitis region hierarchy within the dynamic region block design.
  • Changing QoS settings on axi_noc instances in the dynamic region block design.

The following are prohibited operations:

  • Adding or deleting any IP instances or connections within the Vitis region hierarchy within the dynamic region block design.
  • Adding or deleting connections between the dynamic region and the Vitis region hierarchy.
  • Changes to the address map that modifies any address APERTURES or IP addressing in the Vitis region hierarchy within the dynamic region block design.
  • Project changes that modify the netlist path to the Vitis region hierarchy within the dynamic region block design.

Current limitations of the Simulation flow include the following:

  • The flow is supported for Versal platforms only.
  • The Vivado dynamic region block design must be a block design container, and as a result, base platforms, for example vck190_base, are currently not supported for the flow.
  • You should add IP/logic in the BDC, which needs to be simulated along with AI Engine-PL subsystem.